1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming metal source/drain contact structures for semiconductor devices with gate all around channel structures.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, omega gate devices, gate-all-around (GAA) devices, such as nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. For example, nanowire devices with multiple vertically stacked nanowires, e.g., 2, 3 or 4 nanowires, etc., in the channel region have been developed in an effort to increase the drive current of nanowire devices as compared to the drive current produced by previous nanowire devices that only had a single nanowire structure in the channel region of the device. For example, as compared to a single nanowire device, a nanowire device with three stacked nanowires would be expected to produce a drive current that is approximately three times that of the single nanowire device. However, this anticipated increase in the overall electrical performance of such multiple nanowire devices has not been achieved in practice. It is believed that at least one factor that limits the performance of such multiple nanowire devices is the configuration and/or materials used for the structures that provide electrical contact to the source/drain regions of such multiple nanowire devices.
The present disclosure is directed to various methods of forming metal source/drain contact structures for semiconductor devices with gate all around channel structures that may solve or at least reduce one or more of the problems identified above.